In recent year, the reduction of semiconductor devices and increased packing density have driven the integrated circuits technologies toward deep sub-micron meter range. Various issues arise when the size of the semiconductor devices are scaled down. For example, one of the most traditionally and widely used semiconductor devices is metal oxide semiconductor field effect transistor (MOSFET). As the trend of the integrated circuits, the fabrication of the MOSFET meets some problems, one of the typical problems is short channel effect. The issue is caused by hot carriers that will inject into gate oxide, and which is overcame by the development of lightly doped drain (LDD) structure. In order to manufacture a transistor for 0.1 micron meter ULSI, the gate oxide thickness of MOSFET has to be scaled down less than 2 nm. See "HIGH-FREQUENCY AC CHARACTERISTICS OF 1.5 nm GATE OXIDE MOSFETS, Hisayo Sasaki Momose et al., 1996, IEEE, IEDM 96-105.". In the sub-micron range, the thin gate oxide induces an issue associated with ions that penetrate from doped polysilicon gate into silicon substrate. This is referred to so called initial gate oxide leakage. Thus, the reliability of gate oxide is an important issue for deep sub-micron meter devices. Please see "LEAKAGE CURRENT, RELIABILITY CHARACTERISTIC, and BORON PENETRATION of ULTRA-THIN O.sub.2 OXIDE and N.sub.2 O/NO OXYNITRIDES, Chuan Lin, al., 1996, IEEE, IEDM 96-331.". Chuan has proposed that the N.sub.2 O oxide exhibits lower initial leakage current than O.sub.2 oxide in the ultra-thin oxide region, that is important for low power applications. However, it is hard to fabricate such ultra thin oxide film without pin hole.
Another prior art overcomes aforesaid issue is the use of rapid thermal annealing. The method can effectively suppress the leakage current of dielectric thin films. See "A NOVEL APPROACH LEAKAGE REDUCTION of LPCVD Ta.sub.2 O.sub.5 and TiO.sub.2 FILMS by RAPID THERMAL N.sub.2 O ANNEALING, S. C. Sun et al., 1994, IEEE, IEDM 94-333". To achieve devices with deep sub-micron meter range, the devices have to be scaled proportionally with channel length, source and drain junction, and the shallower source, drain extensions. The requirement of future device is low-energy ion implants with high currents and parallel beams. Plasma immersion doping is relativity simple and can achieve the purpose. See "MEETING the ULTRA-SHALLOW JUNCTION CHALLENGE, Ruth DeJule, SEMICONDUCTOR INTERNATIONAL, 1997". The semiconductor substrate is immersed in a high density plasma, and the devices is formed to have ultra shallow extended source, drain junctions.